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Oct 13, 2010

iMX53EVK DDR2 setting

4. iMX53EVK DDR2 setting.

4.1 EVK rev B hardware connection.

There are four Hynix H5PS2G83AFR(256Mb x 8) on board.




4.2 H5PS2G83AFR parameter (JESD79-2E)






Four Active Window for 1KB page size productstFAW35ns
Refresh to Active/Refresh command timetRFC195ns
Exit self refresh to a non-read commandtXSNRtRFC + 10ns
Exit precharge power down to any non-read
command
tXP2nCK
Exit active power down to read commandtXARD2nCK
Programmable CAS latencyCAS3, 4, 5 and 6nCK
Bin(CL-tRCD-tRP)5-5-5
ACT command to internal read or write delay time (same bank)tRCD5nCK
PRE command period (same bank).tRP5nCK
ACT to ACT or REF command period (same banktRC57.5ns
ACT to PRE command period (same bank).tRAS45ns
WRITE recovery time (same bank).tWR15ns
tRP for a Precharge All command for an 8 Bank device will equal to tRP+1*tCKtRPAtRP + 1nCK
Mode Register Set command cycle (all banks).tMRD2tCK
CAS Write Latency.tCWLCAS - 1nCK
Exit self refresh to a read commandtXSRD200nCK
Internal READ command to PRECHARGE command delay (same bank)tRTP7.5ns
Internal WRITE to READ command delay (same bank)tWTR7.5ns
ACTIVE to ACTIVE command period (all banks).tRRD7.5ns




4.3 iMX53 DDR2 register setting

Please go through “Chapter 19 ESDCTLv2.5 - Enhanced DDR controller” and “Chapter 9 DDR3 PHY” in iMX53RM.pdf for detail information. iMX53 EVK use DDR800, 400Mhz, 1 clk = 2.5ns.

4.3.1 DDR2 timing setting



      Bank Interleaving On, RALAT= 3 cycles additional latency, 8 banks device is being used, DDR2 Enable


      Enable CSD0 and CSD1, row width = 15, column width = 10, burst length = 4, data width = 32bit


     tRFC = 78 ck, tXS = 82 ck, tXP = 2 ck, tXPDLL(tXARD) = 2 ck, tFAW = 14 ck, CAS latency = 5 ck


     tRCD = 5 ck, tRP = 5 ck, tRC = 23 ck, tRAS = 18 ck, tRPA = 1, tWR = 6 ck, tMRD = 2 ck, tCWL = 4 ck


     tDLLK(tXSRD) = 200 cycles, tRTP = 3 ck, tWTR = 3ck, tRRD = 3ck


     Refresh cycles will be triggered in frequency of 32KHz; Refresh Rate.=4 refreshes;

4.3.2 SDRAM Special Command Register (Address 0xBASE_001C (ESDSCR))

This register is used to issue special commands on the external device bus (such as load mode register, manual self refresh, manual precharge etc.). Every write to this register will be interpreted as a command, and a read from this register will show you the last command executed.


4-6
CMD
Command. This field contains the command to be executed:
This field will be automatically cleared after the command will be asserted.
0x0 Normal operation
0x1 Precharge. Can be to a specific bank or to all banks, according to ‘cmd_addr’. If ‘cmd_addr’ equals ‘0x400’
precharge all is issued to the chosen chip select.
Will be issued even if banks are closed. Mainly used for init sequence purpose.
0x2 Auto-Refresh Command
0x3 Load Mode Register Command
0x4 ZQ calibration.
0x5 Precharge all, only if banks open. ‘cmd_addr’ field must be equal to ‘0x400’ in this command.
0x6-0x7 Reserved
Fields CMD_CS, CMD_BA and CMD_ADDR will be used for sending: cs_b,ba,ma signals along with the choosen
command to the memory.



0x63fd901c = 0x04008010 /*Precharge*/
0x63fd901c = 0x00008032 /*write mode reg MR2 with cs0               */
0x63fd901c = 0x00008033 /*write mode reg MR3 with cs0               */
0x63fd901c = 0x00008031 /*write mode reg MR1 with cs0               */
0x63fd901c = 0x0b5280b0 /*write mode reg MR0 with cs0 , with dll_rst0 */
0x63fd901c = 0x04008010 /*Precharge*/
0x63fd901c = 0x00008020 /*Auto-Refresh Command with cs0*/
0x63fd901c = 0x00008020 /*Auto-Refresh Command with cs0*/

About DDR2 Mode Register setting, we need learn something otherwise we would not understand below setting.
0x63fd901c = 0x0a528030 /* BL = 4, CAS latency = 5, write recovery = 6*/
0x63fd901c = 0x03c68031 // OCD Calibration default
0x63fd901c = 0x00468031  // reduced drive strength, enable 50ohm ODT


     DDR2 For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLLdisable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.


      The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while     controlling the state of address pins A0 - A15.
    From 0x63fd901c = 0x0a528030 /* BL = 4, CAS latency = 5, write recovery = 6*/
    we can see (BA1-BA0) is 00b, means MR; (A2-A0) is 010b, means BL=4; (A6-A4) is 101b, means CAS=5; (A11-A9) is 101b, means write recovery equal 6.




4.3.3 iMX53 DDR phy register setting.






4.3.4 DDR2 pin IOMUX setting

     Refer from “Chapter 34 IOMUX Controller (IOMUXC)”,


           30 34 20


4.3.5 DDR2 initialize sequece

      We can find those DDR2 init code in “diag-obds\src\include\mx53\plat_startup.inc”
Don’t forget change the value of  dcd_hdr and write_dcd_cmd base on your real situation.

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