iMX53EVK DDR2 setting

4. iMX53EVK DDR2 setting.

4.1 EVK rev B hardware connection.

There are four Hynix H5PS2G83AFR(256Mb x 8) on board.

MX53	DDR2	MX53	DDR2
DRAM_A[14:0]	A[14:0]	DRAM_D[31:0]	DQ[7:0] x 4
DRAM_SDBA0	BA0	DRAM_SDBA1	BA1
DRAM_SDBA2	BA2	DRAM_SDCKE0	CKE
DRAM_SDWE	WE#	DRAM_CS0	CS#
DRAM_CAS	CAS#	DRAM_RAS	RAS#
DRAM_SDODT0	ODT	DRAM_SDQS[3:0]	DQS x 4
DRAM_SDQS[3:0]_B	DQS# x 4	DRAM_DQM[3:0]	DM/RDQS x 4
DRAM_SDCLK0	CK x 2	DRAM_SDCLK0_B	CK# x 2
DRAM_SDCLK1	CK x 2	DRAM_SDCLK1_B	CK# x 2

4.2 H5PS2G83AFR parameter (JESD79-2E)

Configuration	256 Mb x 8
# of Banks	8
Bank Address	BA0 - BA2
Auto precharge	A10/AP
Row Address	A0 - A14
Column Address	A0 - A9
1 KB	1 KB

Parameter	Symbol	DDR2-800	Units
Four Active Window for 1KB page size products	tFAW	35	ns
Refresh to Active/Refresh command time	tRFC	195	ns
Exit self refresh to a non-read command	tXSNR	tRFC + 10	ns
Exit precharge power down to any non-read command	tXP	2	nCK
Exit active power down to read command	tXARD	2	nCK
Programmable CAS latency	CAS	3, 4, 5 and 6	nCK
Bin(CL-tRCD-tRP)		5-5-5
ACT command to internal read or write delay time (same bank)	tRCD	5	nCK
PRE command period (same bank).	tRP	5	nCK
ACT to ACT or REF command period (same bank	tRC	57.5	ns
ACT to PRE command period (same bank).	tRAS	45	ns
WRITE recovery time (same bank).	tWR	15	ns
tRP for a Precharge All command for an 8 Bank device will equal to tRP+1*tCK	tRPA	tRP + 1	nCK
Mode Register Set command cycle (all banks).	tMRD	2	tCK
CAS Write Latency.	tCWL	CAS - 1	nCK
Exit self refresh to a read command	tXSRD	200	nCK
Internal READ command to PRECHARGE command delay (same bank)	tRTP	7.5	ns
Internal WRITE to READ command delay (same bank)	tWTR	7.5	ns
ACTIVE to ACTIVE command period (all banks).	tRRD	7.5	ns

4.3 iMX53 DDR2 register setting

Please go through “Chapter 19 ESDCTLv2.5 - Enhanced DDR controller” and “Chapter 9 DDR3 PHY” in iMX53RM.pdf for detail information. iMX53 EVK use DDR800, 400Mhz, 1 clk = 2.5ns.

4.3.1 DDR2 timing setting

• ESDCTL Miscellaneous Register (ESDMISC) (0x63fd9018 = 0x000016d0)

      Bank Interleaving On, RALAT= 3 cycles additional latency, 8 banks device is being used, DDR2 Enable

• ESDCTL Control Register (ESDCTL) (0x63fd9000 = 0xc4110000)

      Enable CSD0 and CSD1, row width = 15, column width = 10, burst length = 4, data width = 32bit

• ESDCTL Timing Configuration Register 0(ESDCFG0) (0x63fd900C = 0x4d5122d2)

     tRFC = 78 ck, tXS = 82 ck, tXP = 2 ck, tXPDLL(tXARD) = 2 ck, tFAW = 14 ck, CAS latency = 5 ck

• ESDCTL Timing Configuration Register 1 (ESDCFG1) (0x63fd9010 = 0x92d18a22)

     tRCD = 5 ck, tRP = 5 ck, tRC = 23 ck, tRAS = 18 ck, tRPA = 1, tWR = 6 ck, tMRD = 2 ck, tCWL = 4 ck

• ESDCTL Timing Configuration Register 2(ESDCFG2) (0x63fd9014 = 0x00c70092)

     tDLLK(tXSRD) = 200 cycles, tRTP = 3 ck, tWTR = 3ck, tRRD = 3ck

• Read / WRITE Command Delay. (0x63fd902c = 0x000026d2) Use default value.
• Out of Reset Delays (0x63fd9030 = 0x009f000e)

• SDE_to_RST Not relevant for DDR2,  RST_to_CKE equal 0xE 13 cycles (Jedec value for DDR2) - total of 200 us

• ESDCTL ODT Timing Control Register: ESDOTC(0x63fd9008 = 0x12272000) use default value
• ESDCTL Power Down Control Register: ESDPDC(0x63fd9004 = 0x00030012) use default value.

• Refresh Control Register(0x63fd9020 = 0x00005800)

     Refresh cycles will be triggered in frequency of 32KHz; Refresh Rate.=4 refreshes;

4.3.2 SDRAM Special Command Register (Address 0xBASE_001C (ESDSCR))

This register is used to issue special commands on the external device bus (such as load mode register, manual self refresh, manual precharge etc.). Every write to this register will be interpreted as a command, and a read from this register will show you the last command executed.

4-6 CMD

Command. This field contains the command to be executed: This field will be automatically cleared after the command will be asserted. 0x0 Normal operation 0x1 Precharge. Can be to a specific bank or to all banks, according to ‘cmd_addr’. If ‘cmd_addr’ equals ‘0x400’ precharge all is issued to the chosen chip select. Will be issued even if banks are closed. Mainly used for init sequence purpose. 0x2 Auto-Refresh Command 0x3 Load Mode Register Command 0x4 ZQ calibration. 0x5 Precharge all, only if banks open. ‘cmd_addr’ field must be equal to ‘0x400’ in this command. 0x6-0x7 Reserved Fields CMD_CS, CMD_BA and CMD_ADDR will be used for sending: cs_b,ba,ma signals along with the choosen command to the memory.

0x63fd901c = 0x04008010 /*Precharge*/
0x63fd901c = 0x00008032 /*write mode reg MR2 with cs0               */
0x63fd901c = 0x00008033 /*write mode reg MR3 with cs0               */
0x63fd901c = 0x00008031 /*write mode reg MR1 with cs0               */
0x63fd901c = 0x0b5280b0 /*write mode reg MR0 with cs0 , with dll_rst0 */
0x63fd901c = 0x04008010 /*Precharge*/
0x63fd901c = 0x00008020 /*Auto-Refresh Command with cs0*/
0x63fd901c = 0x00008020 /*Auto-Refresh Command with cs0*/

About DDR2 Mode Register setting, we need learn something otherwise we would not understand below setting.
0x63fd901c = 0x0a528030 /* BL = 4, CAS latency = 5, write recovery = 6*/
0x63fd901c = 0x03c68031 // OCD Calibration default
0x63fd901c = 0x00468031  // reduced drive strength, enable 50ohm ODT


     DDR2 For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLLdisable function, driver impedance, additive CAS latency, ODT (On Die Termination), single-ended strobe, and OCD(off chip driver impedance adjustment) are also user defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.

• DDR2 SDRAM mode register (MR)

      The mode register is written by asserting LOW on CS, RAS, CAS, WE, BA0 and BA1, while     controlling the state of address pins A0 - A15.
    From 0x63fd901c = 0x0a528030 /* BL = 4, CAS latency = 5, write recovery = 6*/
    we can see (BA1-BA0) is 00b, means MR; (A2-A0) is 010b, means BL=4; (A6-A4) is 101b, means CAS=5; (A11-A9) is 101b, means write recovery equal 6.

• DDR2 SDRAM extended mode registers (EMR(#))
• EMR(1)

• The extended mode register(1) is written by asserting LOW on CS, RAS, CAS, WE, HIGH on BA0 and LOW on BA1, while controlling the states of address pins A0 - A15.

From 0x63fd901c = 0x03c68031 // OCD Calibration default

         0x63fd901c = 0x00468031  // reduced drive strength, enable 50ohm ODT

We can see (BA1-BA0) is 01b, means EMR(1); (A6,A2) is 11b, mean ODT=50 ohm; A1 is 1b, means Redueced strength; (A9-A7) is 111b, means OCD Calibration default, after setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000.

• EMR(2)

• The extended mode register(2) is written by asserting LOW on CS, RAS CAS, WE,    HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A15.

4.3.3 iMX53 DDR phy register setting.

• Read Delay Lines Configuration Register(RDDLCTL)(0x63fd9088 = 0x2b2f3031 )
• Write Delay Lines Configuration Register(WRDLCTL)(0x63fd9090 = 0x40363333)
• SDCLK control Register(SDCTRL)(0x63fd9098 = 0x00000f00)

Add 3 logic unit of delay to sdclk to improve EVK DDR max frequency

• DQS gating control register0(DGCTRL0)(0x63fd907c = 0x01310132)
• DQS gating control register1(0x63fd9080 = 0x0133014b)
• ODT control register(0x63fd9058 = 0x00033337) Enable 50ohm ODT
• Measure unit Register1(MUR)(0x63fd90F8 = 0x00000800) Delay line is forced to measure

4.3.4 DDR2 pin IOMUX setting

     Refer from “Chapter 34 IOMUX Controller (IOMUXC)”,

• We set SDQS[3,0], DQM[3,0], CAS, RAS, SDODT[1,0], GRP_ADDDS,GRP_B[0,3]DS, GRP_CTLDS,  DSE feild as 111b too. Set SDCLK_[1,0] DSE feild as 100b.

DSE feild equal 111b,Output impedance depending the ddr_sel value (00 01 10 11). 43

           30 34 20

• DDRMODE_CTL set as DDR2 input type;
• GRP_DDR_TYPE set as DDR_SEL=11b,

DDR2 mode (additional ~100Ohm driver unit is connected, seven driver units are fully       enabled, 20Ohm impedance)

4.3.5 DDR2 initialize sequece

      We can find those DDR2 init code in “diag-obds\src\include\mx53\plat_startup.inc”
Don’t forget change the value of  dcd_hdr and write_dcd_cmd base on your real situation.