Search This Blog

Jul 31, 2011

Porting Android to cell phone.

This is old project from last year, post it here for memory keeping

  1. U-boot setup OK.

    • NOTE: Below u-boot part talking about BBG setting. 
    • In board/freescale/mx51_bbg/flash_header.S
      dcd_array_start:
 magic:   .word 0xB17219E9
 dcd_array_size:  .word dcd_data_end - dcd_array_start - 8
+#if 0
 /* DCD */
 /* DDR2 IOMUX configuration */
 MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x8a0, 0x200)
@@ -107,6 +108,54 @@ MXC_DCD_ITEM(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
 MXC_DCD_ITEM(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
 MXC_DCD_ITEM(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
 MXC_DCD_ITEM(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+#else
+// DDR IOMUX configuration
+// Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+MXC_DCD_ITEM(1, 4, IOMUXC_BASE_ADDR + 0x4b8, 0x000000e7)  // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK       MAX DS
+MXC_DCD_ITEM(2, 4, IOMUXC_BASE_ADDR + 0x4d4, 0x000000e4)  // DQM0 DS high, slew rate slow
+MXC_DCD_ITEM(3, 4, IOMUXC_BASE_ADDR + 0x4d8, 0x000000e4)  // DQM1 DS high, slew rate slow
+MXC_DCD_ITEM(4, 4, IOMUXC_BASE_ADDR + 0x4dc, 0x000000e4)  // DQM2 DS high, slew rate slow
+MXC_DCD_ITEM(5, 4, IOMUXC_BASE_ADDR + 0x4e0, 0x000000e4)  // DQM3 DS high, slew rate slow
+MXC_DCD_ITEM(6, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x000000c4)  // SDQS0 DS high, slew rate slow
+MXC_DCD_ITEM(7, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x000000c4)  // SDQS1 DS high, slew rate slow
+MXC_DCD_ITEM(8, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x000000c4)  // SDQS2 DS high, slew rate slow
+MXC_DCD_ITEM(9, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x000000c4)  // SDQS3 DS high, slew rate slow
+MXC_DCD_ITEM(10, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000004)  // DRAM_B0
+MXC_DCD_ITEM(11, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000004)  // DRAM_B1
+MXC_DCD_ITEM(12, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000004)  // DRAM_B2
+MXC_DCD_ITEM(13, 4, IOMUXC_BASE_ADDR + 0x82c, 0x00000004)  // DRAM_B3
+MXC_DCD_ITEM(14, 4, IOMUXC_BASE_ADDR + 0x878, 0x00000000)  // DRAM_B0_SR
+MXC_DCD_ITEM(15, 4, IOMUXC_BASE_ADDR + 0x880, 0x00000000)  // DRAM_B1_SR
+MXC_DCD_ITEM(16, 4, IOMUXC_BASE_ADDR + 0x88c, 0x00000000)  // DRAM_B2_SR
+MXC_DCD_ITEM(17, 4, IOMUXC_BASE_ADDR + 0x89c, 0x00000000)  // DRAM_B3_SR
+// Configure CS0
+MXC_DCD_ITEM(18, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x83220000) // ESDCTL0: Enable controller
+MXC_DCD_ITEM(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) // ESDSCR: Precharge command
+MXC_DCD_ITEM(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+MXC_DCD_ITEM(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+MXC_DCD_ITEM(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+//MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801a) // ESDSCR: EMR with Half Drive strength
+MXC_DCD_ITEM(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) // ESDSCR
+MXC_DCD_ITEM(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xB3220000) // ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+//          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+MXC_DCD_ITEM(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB02567A9)
+MXC_DCD_ITEM(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000a0100) // ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+// Configure CS1
+MXC_DCD_ITEM(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x83220000) // ESDCTL1: Enable controller
+MXC_DCD_ITEM(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) // ESDSCR: Precharge command
+MXC_DCD_ITEM(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+MXC_DCD_ITEM(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+MXC_DCD_ITEM(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0033801c) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+//MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801e) // ESDSCR: EMR with Half Drive strength
+MXC_DCD_ITEM(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) // ESDSCR
+MXC_DCD_ITEM(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xB3220000) // ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+//          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+MXC_DCD_ITEM(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0xB02567A9)
+MXC_DCD_ITEM(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) // ESDSCR - clear "configuration request" bit
+//MXC_DCD_ITEM(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00f58000) //Delay line write - -11
+#endif
 dcd_data_end:
 image_len:  .word __u_boot_cmd_end - TEXT_BASE
 #endif
    • In drivers/mtd/nand/nand_device_info.c
      static struct nand_device_info nand_device_info_table_type_2[] =
  .tRHOH_in_ns              = -1,
  "HY27UH088G2M",
  },
+  {
+  .end_of_table             = false,
+ .manufacturer_code        = 0xad,
+ .device_code              = 0xb3,
+ .cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
+ .chip_size_in_bytes       = 1LL*SZ_1G,
+ .block_size_in_pages      = 64,
+ .page_total_size_in_bytes = 2*SZ_1K + 64,
+ .ecc_strength_in_bits     = 4,
+ .ecc_size_in_bytes        = 512,
+ .data_setup_in_ns         = 30,
+ .data_hold_in_ns          = 25,
+ .address_setup_in_ns      = 20,
+ .gpmi_sample_delay_in_ns  = 6,
+ .tREA_in_ns               = -1,
+ .tRLOH_in_ns              = -1,
+ .tRHOH_in_ns              = -1,
+ "H8BFS0WU0MCR",
+ },
  {
  .end_of_table             = false,
  .manufacturer_code        = 0x20,
    • include/configs/mx51_bbg_android.h
      -#define CONFIG_MX51_UART1 1
+#define CONFIG_MX51_UART3 1
...
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define MTDIDS_DEFAULT "nand0=nand0"
+#define MTDPARTS_DEFAULT "mtdparts=nand0:0x700000@0x0(BOOT),0x100000@0x700000(MISC),0x1400000@0x800000(RECOVERY),-@0x1c00000(ROOT)"
+#define MTD_ACTIVE_PART "nand0,3"
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_NAND_FW_16BIT 1 /* 1: 16bit 0: 8bit */
...
-/* Enable below configure when supporting nand */
-/* #define CONFIG_CMD_NAND */
+#define CONFIG_CMD_NAND
+#define CONFIG_MXC_NAND
...
-#define CONFIG_FSL_ENV_IN_MMC
-/* #define CONFIG_FSL_ENV_IN_NAND */
+//#define CONFIG_FSL_ENV_IN_MMC
+#define CONFIG_FSL_ENV_IN_NAND
...
-#define CONFIG_SYS_I2C_PORT             I2C1_BASE_ADDR
+#define CONFIG_SYS_I2C_PORT             I2C2_BASE_ADDR
    • In board/freescale/mx51_bbg/mx51_bbg.c, there are too many changes in this file, we list part of it.
      static void setup_uart(void)
 {
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
-    PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
+ unsigned int pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+   PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+ unsigned char buf[4] = { 0 };
+ int reg;
+
+#if 0
  mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
  mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
  mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
@@ -236,6 +240,21 @@ static void setup_uart(void)
  /* enable GPIO1_9 for CLK0 and GPIO1_8 for CLK02 */
  writel(0x00000004, 0x73fa83e8);
  writel(0x00000004, 0x73fa83ec);
+#else
+ mxc_request_iomux(MX51_PIN_DISP2_DAT0, IOMUX_CONFIG_ALT5);
+ mxc_iomux_set_pad(MX51_PIN_DISP2_DAT0, pad);
+ mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, 8);
+ mxc_request_iomux(MX51_PIN_DISP2_DAT1, IOMUX_CONFIG_ALT5);
+ mxc_iomux_set_pad(MX51_PIN_DISP2_DAT1, pad);
+
+ mxc_request_iomux(MX51_PIN_USBH1_NXT, IOMUX_CONFIG_ALT2);
+ reg = readl(GPIO1_BASE_ADDR + 4);
+ reg |= 1 << 28;
+ writel(reg, GPIO1_BASE_ADDR + 4);
+ reg = readl(GPIO1_BASE_ADDR);
+ reg |= 1 << 28;
+ writel(reg, GPIO1_BASE_ADDR);
+#endif
 }
 static void setup_i2c(unsigned int module_base)
 {
  unsigned int reg;
+ unsigned int pad = PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
+   PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST;
+

  switch (module_base) {
  case I2C1_BASE_ADDR:
@@ -460,7 +482,27 @@ static void setup_i2c(unsigned int module_base)
   writel(0x0, reg);
   break;
  case I2C2_BASE_ADDR:
-  /* dummy here*/
+  /* i2c2 SDA */
+  mxc_request_iomux(MX51_PIN_KEY_COL5,
+      IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
+  mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT,
+        INPUT_CTL_PATH1);
+  mxc_iomux_set_pad(MX51_PIN_KEY_COL5,
+      PAD_CTL_SRE_FAST |
+      PAD_CTL_ODE_OPENDRAIN_ENABLE |
+      PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+      PAD_CTL_HYS_ENABLE);
+
+  /* i2c2 SCL */
+  mxc_request_iomux(MX51_PIN_KEY_COL4,
+      IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION);
+  mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT,
+        INPUT_CTL_PATH1);
+  mxc_iomux_set_pad(MX51_PIN_KEY_COL4,
+      PAD_CTL_SRE_FAST |
+      PAD_CTL_ODE_OPENDRAIN_ENABLE |
+      PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU |
+      PAD_CTL_HYS_ENABLE);
   break;
  default:
   printf("Invalid I2C base: 0x%x\n", module_base);

  2. Linux Kernel stays with "Starting kernel ..."

    In kernel_imx/arch/arm/mach-mx5/mx51_3stack.c, function mx51_3stack_timer_init()
    uart_clk = clk_get(NULL, "uart_clk.2");
early_console_setup(UART3_BASE_ADDR,uart_clk);
    And then you can see UART3 output.
    disable CONFIG_USB in imx5_android_defconfig since the mobile phone has not USB host.
    • In drivers/mtd/nand/mxc_nand.c
      @@ -64,6 +64,7 @@ static void mxc_nand_bi_swap(struct mtd_info *mtd)
  struct nand_info *info = this->priv;
  u16 ma, sa, nma, nsa;

+ return;
  if (!IS_LARGE_PAGE_NAND)
   return;

  3. LCD display.

    Connection:
    DISP1_DAT[23:0]   ---> Panel RGB data (difference from 3DS)
DI1_DISP_CLK      ---> DI1_DISP_CLK
DI_GP2            ---> DISPB1_SER_CLK
DI_GP3            ---> DISPB1_SER_DIO
DI_GP4            ---> DISPB1_SER_DIN
DI1_PIN2          ---> DISP1_HSYNC
DI2_PIN3          ---> DISP1_VSYNC
DI1_D1_CS         ---> SER_DISP1_CS
DI1_PIN15         ---> DISP1_DRDY
DISPB2_SER_RS     ---> LCD_nRST       (difference from 3DS)
GPIO1_2_PWM1      ---> Backlight PWM  (difference from 3DS)
EIM_CS3           ---> LCD_EN         (Sharp LCD power supply enable)
    Modify code in kernel_imx/arch/arm/mach-mx5/mx51_3stack.c
    static struct mxc_fb_platform_data fb_data[] = {
    {
-     .interface_pix_fmt = IPU_PIX_FMT_RGB666,
+     .interface_pix_fmt = IPU_PIX_FMT_RGB24,
     },
...

static void __init mxc_board_init(void)
{
...
#if 0
    if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0)
        lcd_data.reset = lcd_reset_to2;
#endif
...
    Modify code in kernel_imx/arch/arm/mach-mx5/mx51_3stack_gpio.c
    //#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL
#if 1
...
#if 1
    {
     MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT1,
     },
#else
    {
     MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT2 | IOMUX_CONFIG_SION,
     (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH |
      PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE),
     MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, INPUT_CTL_PATH3,
     },
#endif
...
void __init mx51_3stack_io_init(void)
    ...
    /* LCD related gpio */
    ...
    gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), "eim_cs3");
    gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3),0);
    gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), 1);
    ...
    Modify code in kernel_imx/drivers/video/mxc/mxcfb_epson_vga.c
    static struct fb_videomode video_modes[] = {
    { /* 480x800 @ 60 Hz, 26Mhz */
     "Sharp-WVGA", 60, 480, 800,  38462, 24, 16, 2, 4, 16, 2,
     FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
     FB_VMODE_NONINTERLACED,
     0,},
};
...
static int lcd_fb_event(struct notifier_block *nb, unsigned long val, void *v)
...
    case FB_EVENT_BLANK:
        if ((event->info->var.xres != 480) ||
-           (event->info->var.yres != 640)) {
+           (event->info->var.yres != 800)) {
            break;
        }

  4. UBIFS image mount.

    • Add UBIFS support in 3stack config.
    • Add 16bit data width support,
      • In kernel_imx/arch/arm/mach-mx5/mx51_3stack.c
        static struct flash_platform_data mxc_nand_data = {
    #ifdef CONFIG_MTD_PARTITIONS
        .parts = nand_flash_partitions,
        .nr_parts = ARRAY_SIZE(nand_flash_partitions),
    #endif
-    .width = 1,
+    .width = 2,
    .init = nand_init,
    .exit = nand_exit,
};
        In function mx51_3stack_io_init() comment below IOMUX part
        #if 0
    if (enable_ata) {
        pin_ptr = ata_iomux_pins;
        num = ARRAY_SIZE(ata_iomux_pins);
    } else if (enable_sim) {
        pin_ptr = sim_iomux_pins;
        num = ARRAY_SIZE(sim_iomux_pins);
    } else {
        pin_ptr = nand_iomux_pins;
        num = ARRAY_SIZE(nand_iomux_pins);
    }

    for (i = 0; i < num; i++) {
        mxc_request_iomux(pin_ptr[i].pin, pin_ptr[i].mux_mode);
        if (pin_ptr[i].pad_cfg)
            mxc_iomux_set_pad(pin_ptr[i].pin, pin_ptr[i].pad_cfg);
        if (pin_ptr[i].in_select)
            mxc_iomux_set_input(pin_ptr[i].in_select,
                    pin_ptr[i].in_mode);
    }
#endif
      • In kernel/drivers/mtd/nand/nand_device_info.c, add below definition in nand_device_info_table_type_2.
        {
    .end_of_table             = false,
    .manufacturer_code        = 0xad,
    .device_code              = 0xb3,
    .cell_technology          = NAND_DEVICE_CELL_TECH_SLC,
    .chip_size_in_bytes       = 1LL*SZ_1G,
    .block_size_in_pages      = 64,
    .page_total_size_in_bytes = 2*SZ_1K + 64,
    .ecc_strength_in_bits     = 4,
    .ecc_size_in_bytes        = 512,
    .data_setup_in_ns         = 30,
    .data_hold_in_ns          = 25,
    .address_setup_in_ns      = 20,
    .gpmi_sample_delay_in_ns  = 6,
    .tREA_in_ns               = -1,
    .tRLOH_in_ns              = -1,
    .tRHOH_in_ns              = -1,
    "H8BFS0WU0MCR",
    },
    • Make Android ubifs image, in vendor/fsl/imx51_3stack/BoardConfig.mk
      TARGET_USERIMAGES_USE_UBIFS :=true
TARGET_MKUBIFS_ARGS := -m 2048 -e 129024 -c 2048 -x none
TARGET_MKUBIFS_ARGS_RECOVERY := -m 2048 -e 129024 -c 100 -x none
TARGET_UBIRAW_ARGS := -m 2048 -p 128KiB -s 512 -O 512 $(PRODUCT_OUT)/ubinize.ini
TARGET_UBIRAW_RECO_ARGS := -m 2048 -p 128KiB -s 512 -O 512 $(PRODUCT_OUT)/ubinize_reco.ini
    • $ make PRODUCT-imx51_3stack-eng will generate android_root.img and android_recovery.img in /out/target/product/imx51_3stack.
    • Use ATK to download image into Nand flash. android_root.img in 0x1c000000, android_recovery.img in 0x00800000.
    • Enter Android GUI. 

  5. UART3 TX/RX not work.

    • In kernel_imx/arch/arm/mach-mx5/board-mx53_evk.h, set #define UART3_MODE MODE_DCE. Because serial.c include this head file.
    • In kernel_imx/arch/arm/mach-mx5/mx51_3stack_gpio.c, comment below code.
      /*
    {
     MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT1,
     (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
      PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
     MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT,
     INPUT_CTL_PATH4,
     },
    {
     MX51_PIN_UART3_TXD, IOMUX_CONFIG_ALT1,
     (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
      PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
     },
     {
     MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT3,
     (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
      PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
     MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT,
     INPUT_CTL_PATH3,
     },
    {
     MX51_PIN_EIM_D24, IOMUX_CONFIG_ALT3,
     (PAD_CTL_HYS_NONE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
      PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST),
     },
 */
    • In kernel_imx/arch/arm/mach-mx5/serial.h, change uart3 relate attribute.
      #define UART3_HW_FLOW           0
#define UART3_DMA_ENABLE        0

  6. Touch screen

    • Connnection
      DISP2_DAT9        --->  Touch_nINT
DISPB2_SER_CLK    --->  Touch_I2C_DAT
DISPB2_SER_DIO    --->  Touch_I2C_CLK
EIM_A16           --->  Touch_nRST1
EIM_CS5           --->  KEY_BACK
    • In kernel_imx/arch/arm/mach-mx5/mx51_3stack_gpio.c
      @@ -874,16 +874,51 @@

  /* LCD related gpio */
  gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), "di1_d1_cs");
- gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
  gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 0);
+#if 0
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
  gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
  gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
+#else
+ mxc_request_iomux(MX51_PIN_DISPB2_SER_DIO, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_DIO, PAD_CTL_DRV_HIGH |
+       PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,1);// Touch I2C CLK
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0");
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 1);
+
+ mxc_request_iomux(MX51_PIN_DISPB2_SER_CLK, IOMUX_CONFIG_ALT4);
+ mxc_iomux_set_pad(MX51_PIN_DISPB2_SER_CLK, PAD_CTL_DRV_HIGH |
+       PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
+ mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,1);// Touch I2C DAT
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), "dispb2_ser_clk");
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), 0);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), 1);
+/*
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), "eim_a16"); // Touch_nRST1
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1);
+*/
+ mxc_request_iomux(MX51_PIN_DISP2_DAT9, IOMUX_CONFIG_ALT5);
+ mxc_iomux_set_pad(MX51_PIN_DISP2_DAT9, PAD_CTL_DRV_HIGH |
+       PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL);
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISP2_DAT9), "disp2_dat9"); // Touch_nINT
+ gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_DISP2_DAT9));

- gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), "eim_cs3");
+ mxc_request_iomux(MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT1);
+ mxc_iomux_set_pad(MX51_PIN_EIM_CS5, PAD_CTL_DRV_HIGH |
+       PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL);
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS5), "eim_cs3"); // power key
+ gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS5));
+#endif
+
+// end
+
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), "eim_cs3"); // LCD power_en
  gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3),0);
  gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), 1);
    • Write GPIO i2c code in /kernel_imx/drivers/input/touchscreen/gpio_i2c.c
    • In kernel_imx/drivers/input/touchscreen/mxc_ts.c, Add driver code to handle touchscreen and keypad handle.

  7. Android BBG config generate UBIFS image.

    In vendor/fsl/imx51_BBG/BoardConfig.mk
    -TARGET_USERIMAGES_USE_EXT2 := true
+TARGET_USERIMAGES_USE_UBIFS :=true
+TARGET_MKUBIFS_ARGS := -m 2048 -e 129024 -c 2048 -x none
+TARGET_MKUBIFS_ARGS_RECOVERY := -m 2048 -e 129024 -c 100 -x none
+TARGET_UBIRAW_ARGS := -m 2048 -p 128KiB -s 512 -O 512 $(PRODUCT_OUT)/ubinize.ini
+TARGET_UBIRAW_RECO_ARGS := -m 2048 -p 128KiB -s 512 -O 512 $(PRODUCT_OUT)/ubinize_reco.ini
    In vendor/fsl/imx51_BBG/AndroidBoard.mk
    #  copy ubinize.ini
ifeq ($(TARGET_USERIMAGES_USE_UBIFS),true)
include $(CLEAR_VARS)
LOCAL_MODULE := ubinize.ini
LOCAL_MODULE_PATH := $(PRODUCT_OUT)
LOCAL_MODULE_CLASS := ETC
LOCAL_SRC_FILES := $(LOCAL_MODULE)
include $(BUILD_PREBUILT)

include $(CLEAR_VARS)
LOCAL_MODULE := ubinize_reco.ini
LOCAL_MODULE_PATH := $(PRODUCT_OUT)
LOCAL_MODULE_CLASS := ETC
LOCAL_SRC_FILES := $(LOCAL_MODULE)
include $(BUILD_PREBUILT)
endif
    In vendor/fsl/imx51_BBG/init.rc
    ...
+    mount ubifs ubi0:system /system
-    mount ext3 /dev/block/mmcblk0p2 /system
...
+    mount ubifs ubi0:data /data nosuid nodev
-    mount ext3 /dev/block/mmcblk0p5 /data nosuid nodev
...
+    mount ubifs ubi0:cache /cache nosuid nodev
-    mount ext3 /dev/block/mmcblk0p6 /cache nosuid nodev

  8. WIFI module enable.

    • Connection
      EIM_A18   --->  2.8V and 1.8V BT power supply
EIM_A23   --->  1.8v and 2.8v wifi power supply
EIM_A22   --->  1.2v wifi power supply
DI1_PIN11 --->  wifi WL_nRST
    • In kernel_imx/arch/arm/mach-mx5/mx51_3stack_gpio.c
      static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = {
+ {
+  MX51_PIN_EIM_A18, IOMUX_CONFIG_GPIO,
+  },
+ {
+  MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO,
+  },
+ {
+  MX51_PIN_EIM_A23, IOMUX_CONFIG_GPIO,
+ },
+ {
+  MX51_PIN_DI1_PIN11, IOMUX_CONFIG_GPIO,
+ },
  /* CSI0 */
...
  { /* TO2 */
  MX51_PIN_DI1_D0_CS, IOMUX_CONFIG_ALT1,
  },
- { /* TO2 */
- MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT1,
- },
+// { /* TO2 */
+// MX51_PIN_DI1_PIN11, IOMUX_CONFIG_ALT1,
+// },
  { /* TO2 */
  MX51_PIN_DI1_PIN12, IOMUX_CONFIG_ALT1,
  },
...
void __init mx51_3stack_io_init(void)
{
...
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), "eim_a18"); // 2.8V and 1.8V BT power supply
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A18),0);
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), "eim_a23"); // 1.8v and 2.8v wifi power supply
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A23),0);
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), "eim_a22"); // 1.2v wifi power supply
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22),0);
+ gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), "di1_pin11"); // wifi WL_nRST
+ gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11),0);
+    // 2.8v high 5ms->1.2V high 5ms -> nRST high
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), 1);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), 1);
+ mdelay(5);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), 0);
+ mdelay(5);
+ gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), 1);
+ printk("wifi power on\n");

  gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3), "eim_cs3"); // LCD power supply enable
  gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3),0);
...
}
    • In kernel_imx/drivers/mmc/host/mx_sdhci.c.
      static int sdhci_probe(struct platform_device *pdev)
{
...
+ /* Add for sdio wifi on 2nd slot */
+ mxc_mmc_force_detect(1);
+
  return 0;
        free:
 dev_set_drvdata(&pdev->dev, NULL);
...
}
    • In kernel_imx/arch/arm/plat-mxc/utmixc.c
      static void usb_utmi_init(struct fsl_xcvr_ops *this)
{
+#if 0
 #if defined(CONFIG_MXC_PMIC_MC13892_MODULE) || defined(CONFIG_MXC_PMIC_MC13892)
  if (machine_is_mx51_3ds()) {
   unsigned int value;
@@ -42,6 +43,7 @@
   pmic_write_reg(REG_USB1, value, 0xffffff);
  }
 #endif
+#endif
}

Posted by at
Labels:

No comments:

Post a Comment

Subscribe to: Post Comments (Atom)